1. Technical Field
The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device, specifically to a semiconductor device including a chip-chip lamination or a chip-wafer lamination.
2. Description of the Related Art
Recently, three-dimensional integration by chip lamination has been disclosed in response to improvement in the integration, enhancement in the functionality, and increase in the speed of semiconductor integrated circuit devices (for example, Unexamined Japanese Patent Publication No. 2006-080145, and ITRS 2007 Assembly and Package Chapter, p. 41).
This is because, in two-dimensional miniaturization as in a conventional system on a chip (SoC) structure, data transmission characteristics are degraded by the increase in wiring resistance caused by reduction in the wiring cross section and the increase in wiring delay caused by increase in the wiring length.
By employing a three-dimensional integration technology of three-dimensionally laminating a semiconductor integrated circuit device, the wiring cross section can be increased and the wiring length can be decreased. In other words, the performance can be improved while the integration degree is increased.
In order to increase the data transmission speed between stacked upper and lower chips, a method is used in which the device surfaces of the upper and lower chips are bonded together (face-to-face) via an external electrode (e.g. micro bump) that is electrically connected to wiring. This method makes the wiring length shortest, and is effective in increasing the transmission speed. Specifically, FIG. 22A shows a conventional, typical wiring lead-out method when the area of the main surface of the lower chip is larger than that of the main surface of the upper chip. FIG. 22B and FIG. 22C show a conventional, typical wiring lead-out method when the area of the main surface of the lower chip is as large as that of the main surface of the upper chip.
FIG. 22A shows the case where the area of the main surface of the lower chip is larger than that of the main surface of the upper chip. FIG. 22B and FIG. 22C show the case where the area of the main surface of the lower chip is as large as that of the main surface of the upper chip. In both cases, the upper chip is bonded to the lower chip via a micro bump, for example. Rewiring 301 (shown by a dotted line in the drawings) led from a central part of the lower chip connects an electrode of the upper chip to a pad of the lower chip.